1. Field of the Invention
The invention relates generally to logic system and more particularly, to a differential current switch logic (DCSL) system.
2. Description of Related Art
Logic systems implemented in complimentary metal oxide semiconductor (CMOS) devices are widely used in many types of computing systems. A useful semiconductor integrated logic circuit is known as "Domino," which is described in detail, for example, in a paper by R. H. Krambeck, et al. entitled "High-Speed Compact Circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, pp. 614-619 (1982). In general, a domino circuit comprises a collection of logic gates, at least some of which deliver logic signals as logic input signals to other gates. This entire circuit is periodically activated by a single clock edge during each period, so that each gate commutes its prescribed logic function during an evaluate phase that occurs once per clock period. Thus, when the circuit is clocked, each gate commutes its prescribed function, one after another, analogously to the falling of a series of dominos.
A differential cascode voltage switch (DCVS) logic system that is suitable for domino is described in U.S. Pat. No. 4,710,650 to Griffen et al. In general, a DCVS gate includes a negative-channel metal oxide semiconductor device (NMOS) evaluation tree and an output stage. The NMOS evaluation tree carries out the logic evaluation, while the output stage translates it to proper logic levels. The NMOS transistor tree generates both true and complementary values at its two output nodes. A design constraint for the NMOS transistor tree is that for each and every possible input combination, a path to ground exists from one of the output nodes. In other words, the NMOS evaluation tree functions as a switching network comprising a pair of complimentary switches, wherein one switch is closed (connected to ground), while the other switch is open.
The difference between various DCVS families is primarily in the output stage. While it is possible to have a static DCVS gate by employing static positive-channel metal oxide semiconductor device (PMOS) pull-ups at the output nodes, clocked DCVS gates are in general preferred because of their better performance. The simplest clocked DCVS gate is the clocked-CVSL gate 10 shown in FIG. 1. The output structure uses PMOS precharge transistors 2 and 4 to pull the inputs 3 and 5 of the inverters 7 and 9 high during the low phase of a clock CLK. The outputs Q and Q# of the inverters 7 and 9 are evaluated in the high phase of the clock. PMOS transistors 6 or 8 provide a weak feedback to reduce deterioration of a high level at one of the inverter inputs 3 or 5.
Higher performance clocked DCVS gates can be built by regeneratively driving the complementary outputs using an inverter loop. FIG. 2 shows a sample set differential logic (SSDL) gate 20, which senses the differential levels set up by an NMOS evaluation tree 12, and regeneratively amplifies them using a cross coupled inverter pair 14 consisting of PMOS transistors 16 and 17 and NMOS transistors 18 and 19. In the prior art SSDL circuit illustrated in FIG. 2, the SSDL gate 20 precharges on the low CLK phase, wherein NMOS transistors 21, 22 and 23 are off. The low CLK signal also allows precharge PMOS transistors 24 and 25 to conduct, charging outputs Q and Q# high. The gate evaluates on the high CLK pulse, with either Q or Q# discharging through NMOS transistor 21 or 23 (depending on the state of the NMOS evaluation tree 12). The cross coupled inverter pair 14 maintains Q and Q# at their differential levels until the next precharge phase.
SSDL is described in more detail by Groijohn and Hoefflinger in an article entitled "Sample-set differential logic (SSDL) for complex high speed VLSI," IEEE J. Solid-State Circuits, Vol. 21, no. 2, pp. 367-369, April 1986. High-performance high-complexity gates are possible with this topology, though SSDL gates generally suffer from high power consumption.
Enabled/disabled CMOS differential logic (ECDL), as proposed in a paper by S. L. Lu, entitled "Implementation of iterative networks with CMOS differential logic," IEEE J. Solid-State Circuits, Vol. 23, no. 4, pp. 1013-1017, August 1988, avoids the high power consumption of SSDL. A prior art ECDL circuit 30 is illustrated in FIG. 3. It employs a precharge low circuitry, and it avoids the static path present in the evaluate phase of SSDL. The ECDL circuit 30 precharges on the positive CLK pulse, with PMOS transistor 33 off, allowing the outputs Q and Q# to discharge through NMOS transistors 31 and 32. On the low CLK pulse, PMOS transistor 33 turns on, allowing V.sub.cc to charge either Q or Q#, depending on the state of the NMOS evaluation tree 12.
Each of the above prior art circuits precharges its outputs during one level of the clock and evaluates during the other. The internal nodes in the NMOS evaluation tree switch over a voltage which is equal to the supply voltage less the threshold voltage of the NMOS device. Hence, gate power dissipation increases with an increase in the complexity of the NMOS evaluation tree. In addition, the rising output is slow because of the need to charge up the internal nodes of the NMOS evaluation tree. For these reasons, circuit design techniques have largely overlooked DCVS circuits in favor of traditional CMOS styles, primarily because the high activity of DCVS gates causes them to compare unfavorably with respect to conventional CMOS implementations from a power perspective. Further, the need to route differential signals (resulting in high signal activity), and the high clock load of clocked DCVS gates are known disadvantages compared to conventional CMOS logic gates. However, DCVS gates have potential advantages as compared to standard CMOS NAND(NOR) implementations.
High complexity, high fan-in gates are possible. Complex gates can be implemented with lower transistor count. Certain clocked DCVS families have very low propagation delay for large, complex gates. Clocked DCVS styles often integrate both the sequential and combinatorial portions into a single complex gate. This style of logic is hence suitable for high-speed VLSI. PA1 Both true and complementary outputs are available. This makes completion of gate evaluation easy to detect. It is this reason that makes DCVS gates the logic family of choice for implementing self-timed circuits. PA1 In common with dynamic logic, gate input loading is very light and consists of few NMOS transistors.
The high power consumption of DCVS gates is a definite hindrance toward their greater acceptance. The power consumed by a DCVS gate can be subdivided into the power consumed because of outputs switching and the power consumed because of switching at the gate internal nodes. As the gate complexity increases, the number of internal nodes switched in the NMOS evaluation tree increases. Hence, power dissipation due to switching in internal nodes is a non-negligible factor of the total gate power.
Differential current switch logic (DCSL), a class of clocked DCVS logic circuits, has been developed in an attempt to limit internal voltage swings and improve power performance of previous DCVS. DCSL is described in "Differential Current Switch Logic: A Low Power DCVS Logic Family," IEEE J. Solid State Circuits, Vol. 31, no. 7, July 1996, by D. Somasekhar and K. Roy. FIG. 4 illustrates a simplified block diagram of a DCSL switch 40. The DCSL switch 40 includes an NMOS evaluation tree 12 and a DCVS-family output state network 41, such as those illustrated in FIGS. 1-3. In addition, two NMOS transistors 42 and 43 are coupled in series between the DCVS-family output state network 41 and the NMOS evaluation tree 12, with the gates of the transistors 42 and 43 cross-coupled to the state outputs Q and Q#.
As with the DCVS circuits illustrated in FIGS. 1-3, the outputs Q and Q# precharge to a given level. During the evaluate phase, one output sees a path to ground through the NMOS evaluation tree 12 and evaluates low, with the complementary output evaluating high. The transistors 42 and 43 function to isolate the outputs Q and Q# from the NMOS evaluation tree 12 following evaluation. Assume Q evaluates low and Q# evaluates high. The low value from Q is cross-coupled to the gate of one transistor 43, keeping it off, thereby isolating the high output Q# from the NMOS evaluation tree 12 and protecting the high value from falling low, even if a path to ground through the NMOS evaluation tree 12 is established following evaluation. Further, this ensures that no static path exists from the voltage supply V.sub.cc to ground, reducing node voltage swings in the NMOS evaluation tree 12.
A schematic diagram of an embodiment of a prior art DCSL circuit 40 is shown in FIG. 5. The DCSL gate 40 of FIG. 5 is a "precharge high" gate, in that the gate outputs Q and Q# both charge high during the precharge phase. It consists of a voltage supply V.sub.cc, an NMOS evaluation tree 12, a cross coupled inverter pair 44 (PMOS transistors 46 and 48, and NMOS transistors 50 and 52), and precharge transistors 54 and 56. A clock signal CLK is coupled to the gates of the precharge transistors 54 and 56, and also to the gates of NMOS transistors 58, 60 and 62. NMOS isolation transistors 42 and 43 are cross coupled to outputs Q and Q#. In other words, the NMOS isolation transistor 42 has its drain terminal coupled to output Q and its source terminal connected to a first output 68 of the NMOS evaluation tree 12 through the clocked transistor 58, with the gate of the NMOS transistor 42 coupled to output Q#. Similarly, the NMOS transistor 43 has its drain terminal coupled to output Q# and its source terminal connected to a second output 70 of the NMOS evaluation tree 12 through the clocked transistor 62, with the gate of the NMOS transistor 43 coupled to Q.
The NMOS evaluation tree 12 further includes a plurality of inputs. The NMOS evaluation tree functions such that for every possible input combinations, there is a single path to ground from one of the output nodes 68 and 70. In other words, the NMOS evaluation tree functions as a switching network comprising a pair of complimentary switches, S1 and S2, wherein when one switch (S1 in FIG. 5) is closed (connected to ground), the complimentary switch S2 is open.
Operation of the DCSL gate 40 starts with the CLK signal low, turning off the NMOS transistors 58, 60 and 62, while turning on the precharge PMOS transistors 54 and 56. V.sub.cc charges the outputs Q and Q# high through the precharge PMOS transistors 54 and 56. The evaluate phase begins with stable inputs to the NMOS evaluation tree 12 and the CLK signal going high. For purposes of illustration, assume that the inputs to the NMOS evaluation tree 12 cause a path to exist from output 68 to ground (S1 closed and S2 open). The CLK signal going high switches the NMOS transistors 58, 60 and 62 on, while Q and Q# being high (from the precharge phase) ensure that the NMOS isolation transistors 42 and 43 are switched on.
The outputs Q and Q# discharge toward ground through NMOS transistors 58, 60, and 62. The discharge of Q and Q# is not symmetrical because the NMOS evaluation tree assures that only one of the outputs, Q, has a stronger path to ground. This causes Q to fall faster than Q#. The cross-coupled inverter 44 functions as a sense-amplifier and boosts the output voltage differential. Once the inverter switch threshold is crossed by Q, Q# swings high. The low going transition of Q disconnects the NMOS evaluation tree 12 from Q# by progressively cutting off the transistor 43. Hence, the rising node Q# is isolated from the NMOS evaluation tree 12. This action limits the charge up of internal nodes in the NMOS evaluation tree 12. This is unlike other DCVS circuits where the NMOS pull-down tree is never disconnected from the outputs Q and Q#. DCVS circuits charge the internal nodes of the NMOS evaluation tree 12 up to V.sub.cc -V.sub.tn, where V.sub.cc is the supply voltage (5V) and Vtn is the threshold voltage of the NMOS device (of the order of 1V). In contrast, DCSL charges internal nodes to much smaller voltages. Simulations show that internal node voltage swings for DCSL are of the order of 1V. The gate comes to rest in a state with Q low and Q# high.
On completion of evaluation, the fact that the high output (Q# in the FIG. 5) is disconnected from the NMOS evaluation tree assures that flirter changes in inputs do not propagate to the output Q#. This is unlike CMOS logic styles, in which changes in the inputs of clocked logic cause dc through-currents, or the gate's state output is destroyed. Strict adherence to the design constraint of building DCVS NMOS evaluation trees is no longer required. Gate inputs may cause paths to ground in both halves of the NMOS evaluation tree 12. However, assuring that one of the paths has a stronger pull-down than the other allows the DCSL gate to evaluate its inputs. On completion of evaluation, no static current paths from V.sub.cc to ground exist.
While a prior art DCSL gate 40, such as the circuit of FIG. 5, reduces the power requirement as compared to standard DCVS gates, shortcomings exist. In a known DCSL gate 40, such as in FIG. 5, the outputs Q and Q# are directly fed back to the inverter loop 44 during both the precharge phase and the evaluate phase. This strong positive feedback can upset the operation of the gate 40 if the two halves are not balanced. The circuit will not only amplify differential currents arising from the NMOS evaluation tree 12, but also any other current differentials such as unbalanced output loads. Therefore, prior art DCSL circuits are not robust and they are sensitive to load imbalances at the outputs Q and Q#.
Moreover, in the circuit of FIG. 5, the outputs Q and Q# are both charged high. At the beginning of the evaluate phase, both outputs have a path to ground through the transistor 60; thus, both outputs begin to fall low. The additional path to ground through the NMOS evaluation tree 12 for one output causes that output to fall faster, and the cross coupled inverter 44 boosts the output voltage differential in the correct direction. While this causes the outputs Q and Q# to eventually evaluate to their proper complementary levels, the initial discharge of the output that ultimately swings high causes a voltage spike at the output.
The output voltage spike of known DCSL circuits causes several problems. First, it causes interference problems with other circuits. For example, it would be difficult to drive a static CMOS gate with a prior art DCSL circuit, as illustrated in FIG. 5. Next, the discharge/recharge action of the high output increases power consumption, which is a primary concern. Additionally, the voltage spike degrades operation at low voltage levels. Prior art DCSL gate performance degrades with increasing threshold voltage as a fraction of supply voltage (V.sub.tn /V.sub.cc).
These factors make implementation of known DCSL gates difficult in practical designs. Thus, a need exists for a robust DCSL gate capable of operation at lower voltages that is suitable for implementing high speed clocked CMOS circuits.